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Portfolio · IC Design & Semiconductor

Nguyễn Ngọc Sơn

Designing at the scale of nanometres.

A portfolio on integrated circuit design and semiconductor technology — from a line of RTL to structures etched in silicon.

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Education
FPT University, Hanoi
IELTS
6.0
TOEIC
750

01 / Profile

Where logic becomes physics.

Portrait · die window

I'm Nguyễn Ngọc Sơn. This portfolio collects my work in integrated circuit design and semiconductor technology — the projects, the design flow behind them, and the details that make a chip work.

Datasheet · personalRev. 2026
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02 / The IC design flow

From specification to silicon.

Seven stages every digital chip passes through on its way to the fab.

  1. Stage 01

    Specification

    Every chip starts as a contract: what it must do, how fast it must run, how much power it may burn and how much silicon it may occupy.

    Function · Performance · Power · Area

  2. Stage 02

    Architecture

    The design is partitioned into blocks — control, datapath, memory, interfaces — and the trade-offs between them are settled before any logic is written.

    Partitioning · Interfaces · Trade-offs

  3. Stage 03

    RTL design

    Behaviour is described at register-transfer level in Verilog, SystemVerilog or VHDL — hardware written as code, one clock edge at a time.

    Verilog · SystemVerilog · VHDL

  4. Stage 04

    Functional verification

    Testbenches, assertions and coverage try to break the design in simulation, long before silicon gets the chance.

    Testbench · Assertions · Coverage · UVM

  5. Stage 05

    Logic synthesis

    RTL is mapped onto a standard-cell library and optimised against timing constraints, producing a gate-level netlist.

    Standard cells · SDC · Netlist

  6. Stage 06

    Physical design

    Floorplanning, placement, clock-tree synthesis and routing turn the netlist into polygons on stacked metal layers.

    Floorplan · Placement · CTS · Routing

  7. Stage 07

    Signoff & tape-out

    Static timing, DRC, LVS and power checks must all come back clean. Then the GDSII layout is released to the fab.

    STA · DRC · LVS · GDSII

03 / Projects

Work, die by die.

04 / Curriculum vitae

Curriculum vitae.